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summary tc90107 f g page 1 rev.1.00 20 15/11/24 toshiba cmos digital integrated circuit silicon monolithic TC90107FG single channel video decoder th e TC90107FG is a single chip ic th at converts analog video signal to digital video signal. (itu - r b t. 6 5 6 ) additionally , the TC90107FG has one 10bit a d c as analog input interface, and has one 3 - line y/c separation , and multi - sy stem color decoder . 1. features 1. analog video signal input : cvbs 2. adaptive multi - color de coder (1ch) 3. s ync processing / vi deo system detection 4. 1 0bit adc ( 1ch) 5. analog agc (sync agc + peak agc) 6. lpf circuit for input analog video signal 7. y/c separation : 3 - line ycs (ntsc/pal) band p ass f ilter (secam) 8. picture process y: hv enhance, v enhance, lti, sharpness, noi se cancel, dynamic gamma correction, static gamma correction contrast, brightness c : tof, acc, color gain, color offset, cti, noise cancel, tint, color management, color gain correction linked to y - gamma 9. f unction h orizontal aberration correction, data slice(wss / video - id / cc), s/n detection 10. digital video signal output : itu - r bt.656 11. i 2 c - bus control 12. regulator circuit (3.3 v input / 2.5 v output) 13. package : lqfp 64 pin (0.50 mm pitch) 14. power supply : 3.3 v, 2.5 v, 1.5 v 15. operation temperature : - 40 c to 85 c lqfp 64-p-1 010 - 0.50e weight : 0. 4 0 g ( typ . ) ?2015 toshiba corporation
summary tc90107 f g page 2 rev.1.00 20 15/11/24 2. block diagram * 1 : reg ulator output 2.5 v is not connected in the inside of ic. w hen it use built in regurator, i t connected on board. cvbs 1 cvbs 2 s w lpf gca 10 bit adc 3 line - comb ycs sync sep . hv timing multi color decoder color system detection vbi slicer cc / video -id 1/ wss hv enhancer lti sharpness noise canceller cti color - gain noise canceller itu - bt 656 encode clock generator i2 c bus scl sda regulator lvttl y c color management tint aberration correction color gain color offset dynamic - gamma contrast brightness cvbs 3 cvbs 4 27 mhz 3.3v 2.5v *1
summary tc90107 f g page 3 rev.1.00 20 15/11/24 3. pin layout 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 cvbs1 vrt monitor gcavref notused advdd1 reg25outa notused regvssa regvdd33a regvref notused vss7 xovdda xout xin 49 advss1 vss6a 32 50 cvbs2 notused 31 51 adbias vdd3a 30 52 vrm iovdd2a 29 53 advss2 notused 28 54 advdd2 data0 27 55 notused data1 26 56 notused vss5 25 57 cvbs3 data2 24 58 vrb data3 23 59 cvbs4 vss4a 22 60 notused data4 21 61 sda data5 20 62 scl data6 19 63 notused vss3 18 64 vss8a data7 17 slvsel reset vdd1a vss1 test0 test1 con2 con1 con0 notused vss2a clk notused iovdd1a notused vdd2a 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 top view
summary tc90107 f g page 4 rev.1.00 20 15/11/24 4. pin description no. pin name i/o function tolerable voltage [ v] circuit treatment when not in use 1 slvsel i i 2 c slave address select 3.3 digital full - time use 2 reset i system reset ( reset is low. ) 5 digital gnd 3 vdd 1a dvdd power supply for logic : 1.5v 1 .5 digital 1.5 v 4 vss 1 dvss gnd for logic 0 digital gnd 5 test0 i test terminal 0 3.3 digital gnd 6 test1 i test terminal 1 3.3 digital gnd 7 con2 o timing pulse output 2 3.3 digital o pen 8 con1 o timing pulse output 1 3.3 digital o pen 9 con0 o timi ng pulse output 0 3.3 digital open 10 n otused n.c. n ot connect - digital full - time o pen 11 vss2 a dvss gnd for logic 0 digital gnd 12 clk o clk output 3.3 digital open 13 n otused n.c. not connect - digital full - time o pen 14 iovdd1 a iovdd33 power suppl y for io : 3.3 v 3.3 digital 3.3 v 15 n otused n.c. not connect - digital full - time o pen 16 vdd2 a dvdd power supply for logic : 1.5 v 1.5 digital 1.5 v 17 data7 o digital data output 7 3.3 digital open 18 vss3 dvss gnd for logic 0 digital gnd 19 data6 o digital data output 6 3.3 digital open 20 data5 o digital data output 5 3.3 digital open 21 data4 o digital data output 4 3.3 digital open 22 vss4 a dvss gnd for logic 0 digital gnd 23 data3 o digital data output 3 3.3 digital open 24 data2 o digital data output 2 3.3 digital open 25 vss5 dvss gnd for logic 0 digital gnd 26 data1 o digital data output 1 3.3 digital open 27 data0 o digital data output 0 3.3 digital open 28 n otused n.c. not connect - digital full - time o pen 29 iovdd2 a iovdd33 power supply for io : 3.3 v 3.3 digital 3.3 v 30 vdd3 a dvdd power supply for logic : 1.5 v 1.5 digital 1.5 v 31 n otused n.c. not connect - digital full - time open 32 vss6 a dvss gnd for logic 0 digital gnd
summary tc90107 f g page 5 rev.1.00 20 15/11/24 no. pin name i/o function tolerable voltage [v] circuit treatment when not in use 33 xin i x?tal osc circuit input terminal 3.3 digital full - time use 34 xout o x?tal osc circuit output terminal 3.3 digital full - time use 35 xovdd a xovdd power supply for x?tal : 3.3 v 3.3 digital 2.5 v or 3.3 v 36 vss 7 dvss gnd for logic 0 digital gnd 37 n otused n.c. not connect - digital open 38 regvref bias v oltage relay for internal reg ulator 2.5 analog gnd via 0.1 f 39 regvdd33 a avdd33 power supply for internal reg ulator ( for adc block ) 3.3 analog 3.3 v 40 re gvss a avss analog gnd for internal reg ulator 0 analog gnd 41 n otused n.c. not connect - digital full - time open 42 reg25out a o output of internal reg ulator ( for adc) 2.5 analog open 43 advdd1 avdd25 power supply for adc & gca : 2.5 v 2.5 analog 2.5 v 4 4 n otused n.c. not connect - digital full - time open 45 gcavref bias reference voltage output for gca 2.5 analog gnd via 0.1 f 48 cvbs1 i cvbs input 1 2.5 analog open 49 advss1 avss analog gnd for adc/gca 0 analog gnd 50 cvbs2 i cvbs input 2 2.5 analog open 51 adbias bias reference voltage of adc 2.5 analog full - time use 52 vrm bias reference middle voltage of adc 2.5 analog full - time use 53 advss2 avss analog gnd for adc/gca 0 analog gnd 54 advdd2 avdd25 power supply for adc & gca : 2.5 v 2.5 analog 2.5 v 55 n otused n.c. not connect - digital full - time open 56 n otused n.c. not connect - digital full - time open 57 cvbs3 i cvbs input 3 2.5 analog open 58 vrb bias reference bottom voltage of adc 2.5 analog full - time use 59 cvbs4 i cvbs inp ut 4 2.5 analog open 60 n otused n.c. not connect - digital full - time open 61 sda i/o i 2 c data input 5 digital full - time use 62 scl i i 2 c clock input 5 digital full - time use 63 n otused n.c. not connect - digital open 64 vss8 a dvss gnd for logic 0 di gital gnd
summary tc90107 f g page 6 rev.1.00 20 15/11/24 5. function ? multi - color decoder ? output format is itu - r bt.656 ? the tc9010 7 fg has many video quality improving function, such as hvd - enhancer, dynamic - gamma, color - management and so on. ? horizontal nonlinearly scaling (horizontal fish - eye correctio n, horizontal trapezoid correction and so on) ? vbi data slicer function (closed caption, video - id and wss are available. ) ? regulator circuit (3.3 v input / 2.5 v output) for adc circuit by external connection. 5.1 analog video signal input 5.1.1 anal og video signal input amplitude level the tc9010 7 fg has one 10bit adc for 1ch cvbs input. the dynamic range of th is adc is designed in avdd*0.4 with the normal input dynamic range being 1 vp - p (avdd = 2.5 v). be sure to use 0.7 vp - p with 140ire input when using cvbs as the recommended reference input amplitude. the tc9010 7 fg has agc function for cvbs input : however, to use the agc cover range effectively we recommend that you use 0.7 vp - p with 140ire input for the input amplitude. 5.1.2 analog video signal refe rence input level 1) reference input level for composite video signal when 100% white (i.e. composite video input) composite video signal input level (ex : 75% color bar ) 100 - 40 0 20 40 60 80 - 20 < ire > 0 . 7 vp - p 5.1.3 agc ( auto gain control ) function agc function is u sed for composite video signal by gca (gain control amp) circuit and digital agc function. agc function has two mode : a uto gain mode and manual gain mode. i t is possibl e to use 1.0 vp - p input amplitude by gca function. 5.1.4 lpf function TC90107FG has l pf for a nti - aliasing in front of gc a block . it is possible to select on or thr ough mode . ? system : fourth - order butter worth filter ? frequency characteristic : -1 db@6 mhz, -14 db@13.5 mhz
summary tc90107 f g page 7 rev.1.00 20 15/11/24 5.2 digital output signal (outsel block) 5.2.1 output signal format the TC90107FG o utput is the itu - r bt.656. pedestal level for y signal is 16 lsb. center level for cb and cr signal is 128 lsb. notice TC90107FG use the free - run clock system. therefore, the number of sample between eav and sav occur the increase and decrease. it m ust take the data from sav start . if mistake , it will occur the jitter. you must design , it is not affected by the number of sample in blanking. z the system needs not to affect in irregular eav and sav about itu -r b t .656 . the uptake st art of picture must be sav. z when it is not suitable for itu -r b t .656 , it deeds to confirm in combination with the following signals . 1) hd 2) vd 3) data enable 4) field flag (odd/even) 5) u/v flag (cbcr select) TC90107FG can o utput three timing si gnals chose n by register at timing output terminal(con[2 : 0] ). normally the number of sample are increase a nd decrease in period of blanking . last line next line period of blanking data
summary tc90107 f g page 8 rev.1.00 20 15/11/24 5.2.1.1. input of 525i/60hz 525 1 2 3 4 5 6 7 8 9 10 19 20 hdout odd field vdout odd / even field 1 vdout odd / even field 1 3h 19 h synchronous through mode itu - r bt . 656 conformity mode 263 264 265 266 267 268 269 270 271 272 273 283 284 hdout vdout odd / even field 2 vdout odd / even field 2 3h 19 h even field 4 line 266 . 5 line 266 line eav 4 line eav 21 22 285 264 line eav 283 line eav 20 line eav 1 line eav 262 de ( default ) de ( default ) up to 260 (240 line ) up to 522 (240 line ) output signal output signal synchronous through mode itu - r bt . 656 conformity mode 5.2.1.2. input of 625i/50hz odd field o utput through itu - r b t. 656 mode even field o utput through itu - r b t. 656 mode mode mode 621 622 623 624 625 1 2 3 4 5 6 23 24 v eve ie 1 v eve ie 1 2.5 24 309 310 311 312 313 314 315 316 317 318 319 336 337 v eve ie 2 v eve ie 2 2.5 25 1 313 .5 line 313 line eav 23 line eav 311 line eav 336 line eav de ( default ) up to 310 (288 line ) de ( default ) up to 622 (288 line ) 22 335 odd field synchronous through mode itu - r bt . 656 conformity mode even field output signal output signal synchronous through mode itu - r bt . 656 conformity mode odd field o utput through itu - r b t. 656 mode mode even field o utput through itu - r b t. 656 mode mode
summary tc90107 f g page 9 rev.1.00 20 15/11/24 5.2.2 timing pulse output c on[ 2 : 0] pin (terminal no.7, 8, 9) are output terminal. out put signal can select by register. 1. de (d ata enable) signal de indicates horizontal and vertical enable picture area for output video signal. de signal is the signal that is high status at active video period, and low status at blanking period. 2. hd signa l hd signal indicates the horizontal sync pulse synchronized with output video signal . setting : pulse width, pulse polarity, phase delay 3. vd signal vd signal indicates the vertical sync pulse synchronized with output video signal . setting : pulse wi dth, pulse polarity, phase delay 4. field signal field signal indicates odd/even switch pulse synchronized with output video signal. field signal is the signal that is high status at even field, and low status at odd field, when default setting. polarity of field signal inverts by register [fldo_pole]. 5. uvflg signal uvflg signal indicates cb/cr switch pulse for 4:2:2 format signal. polarity of uvflg signal inverts by register [uvrev]. 5.3 regulator circuit t he regulator circuit of 2.5 v output (3.3 v in put) for adc circuit is built in ic . to use regulator output voltage, it is necessary to connect the output terminal of regulator circuit to the power supply input terminal of an adc circuit in ic exterior. in addition, please do not use the built - in reg ulator circuit other than the purpose of this ic operation. when it is no use the built - in reg ulator , do not supply 3.3 v at 39 pin. regulator circuit the input terminal which regulator output 3.3 v input terminal 2.5 v output terminal reg vdd33 a (39 pi n) reg25out a (42 pin) ad vdd1 (43 pin) a d vdd2 (54 pin)
summary tc90107 f g page 10 rev.1.00 20 15/11/24 6. absolute m aximum rating the absolute maximum ratings are rated values which must not be exceeded during operation, even for an instant. exceeding the absolute maximum rating s may result in destruc tion, degradation or other damage to the ic and other components. when designing applications for this ic, be sure that none of the absolute maximum rating values will ever be exceeded. characteristics terminal n o. symbol rating unit power voltage1 ( 1.5 v ) 3, 16, 30 vdd 1 - 0.3 to vss + 2 .0 v power voltage2 ( 2.5 v ) 43, 54 vdd 2 - 0.3 to vss + 3.5 v power voltage3 ( 3.3 v ) 14, 29, 35, 39 vdd 3 - 0.3 to vss + 3.9 v input voltage ( 2.5 v ) 48, 50, 57, 59 vin 2 - 0.3 to v dd2 + 0.3 v input voltage ( 3.3 v ) 1, 33 v in 3 - 0.3 to v dd3 + 0.3 v input voltage (3.3 v system, 5 v withstand voltage) 2, 61, 62 vin4 (note.1) - 0.3 to vss + 5.5 v potential difference between power pins (between 1.5 v system power pins) - vdg1 (note.2) 0.3 v potential difference between power pin s (between 2.5 v system power pins) - vdg2 (note. 2 ) 0.3 v potential difference between power pins (between 3.3 v system power pins) - vdg3 (note. 2 ) 0.3 v power dissipation - pd (note. 3 ) 1739 mw storage temperature - tstg - 40 to 125 c note1 : the withstand voltage for pins (sda, scl , reset ) is 5 v. note2 : for each of 1.5 v and 2.5 v and 3.3 v, system power supply terminal is made into the same voltage. the maximum potential difference should not exceed rating for all power supply terminals then. in addition, potential difference between all v ss terminal must be under 0.01 v in this status. note 3 : if you intended to use a temperature higher than ta = 25c, reduce by 17.39 mw per one degree (c) increase. the case of ta = 8 5 c , power dissipation is 696 mw. power dissipation [mw] >?>y>>>a>>>>>y>>y>>>>>>>>0?? 696 0 1739 0 1000 2000 0 25 50 75 100 125 v 79 0 power dissipation characteristics power dissipation pd [mw] ambient air temperature
summary tc90107 f g page 11 rev.1.00 20 15/11/24 7. operating range the tc9 0107 fg is not guaranteed to function correctly if it is used outside its specified power voltage rage (1.5 v system power : 1.40 v to 1.60 v, 2.5 v system power : 2.3 v to 2.7 v, 3.3 v system power : 3.0 v to 3 .6 v). please use within the specified operating conditions. if you temporarily leave and then return to the specified operating conditions, this ic?s conditions will change, and so it is necess ary to reset the ic?s power to continue using it correctly within the specified operating conditions. characteristics terminal n o. symbol min typ. max unit power voltage of digital block 3, 16, 30 vdd - d 1.4 1.5 1.6 v power voltage of i/o block ( *1 ) 14, 29 vdd - io 3.0 3.3 3.6 v power voltage of regulator block ( *1 ) 39 vdd - reg 3.0 3.3 3.6 v power voltage of xo block ( *2 ) 35 vdd - xo 2.3 3.3 3.6 v power voltage of analog block 4 3, 54 vdd - ad 2.3 2.5 2.7 v operating templature t opr - 40 - 85 c (*1) if possi ble, please set i/o power supply voltage and regulator power supply voltage into the potential. (*2) when you connect xo power supply to 2.5 v power supply, if possible, please use the potential with analog power supply voltage . although connecting with 3.3 v power supply is also possible, please set i/o power supply voltage and regulator power supply voltage as the potential in that case.
summary tc90107 f g page 12 rev.1.00 20 15/11/24 8. electrical characteristic 8.1 dc characteristic ( ta = 2 5 c , vdd1 = 1.50 0.1 v, vdd2 = 2.5 0 0.2 v, vdd3 = 3.30 0.3 v) charact erisitc terminal n o. . symbol min typ. max unit note power supply current (*4) 3, 16, 30 idd1 (1.5 v) - - 75 ma 43, 54 idd2 (2.5 v) - - 75 ma when a built - in regulator was not used but 2.5 v power supply is suppl ied from the out side. 14, 29, 35, 39 idd3 - 1 (3.3 v) - - 30 ma when a built - in regulator was not used but 2.5 v power supply is supplied from the out side. idd3 - 2 (3.3 v) - - 105 ma when a built - in regulator is used. input voltage 1, 33 vih vdd3 x 0. 8 - vdd 3 v i/o input terminal of 3.3 v system. 2, 61, 62 i/o input terminal of 5.0 v system. 1, 33 vil vss - vdd3 x 0.2 v i/o input terminal of 3.3 v system. 2, 61, 62 i/o input terminal of 5.0 v system. input current 1, 33 iih - 10 - 10 a i/o input terminal of 3.3 v system. 2, 61, 62 i/o input terminal of 5.0 v system. 1, 33 iil - 10 - 10 a i/o input terminal of 3.3 v system. 2, 61, 62 i/o input terminal of 5.0 v system. output voltage 7, 8, 9, 12, 17, 19, 20, 21, 23, 24, 26, 27, 34 v oh vdd3 - 0.6 - vdd3 v i/o out put terminal of 3.3 v system. w hen load current : - 4 ma v ol vss - 0.4 v i/o out put terminal of 3.3 v system. w hen load current : + 4 ma (*4) power consumption (w) changes the calculation method by whether a buil t - in regulator is used or it is not used. when a built - in regulator is used : sum total o f idd1 and idd3 -2 when a built - in regulator is not used : sum total of idd1, idd2, and idd3 -1
summary tc90107 f g page 13 rev.1.00 20 15/11/24 9. package weight : 0. 4 0 g ( typ . ) lqfp64 - p - 1010 - 0.50e unit : mm
summary tc90107 f g page 14 rev.1.00 20 15/11/24 10. revision history date revision content s 201 5 / 11 / 2 4 1.00 first edition
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